1. Field of the Invention
The present invention relates to non-volatile, high density, integrated circuit memory devices, and more particularly to such memory devices based upon phase change material such as chalcogenides.
2. Description of Related Art
Chalcogenides have been utilized in the formation of memory cells for integrated circuit memory devices. Representative prior art patents in this field include Reinberg, U.S. Pat. No. 5,789,758; Harshfield, U.S. Pat. No. 6,077,729; Wolstenholme, et al., U.S. Pat. No. 6,153,890, Ovshinsky, U.S. Reissue Pat. No. RE37,259 (Reissue of U.S. Patent No. 5,687,112), and many others.
Chalcogenides used for integrated circuit memory devices are materials characterized by more than one solid-state phase, and which can be switched between such phases using the application of heat caused for example by electrical current or optical pulses. Memory cells which include a chalcogenide element are arranged in an array which can be addressed using conventional word lines/bit line addressing schemes common in integrated circuit memories. The state of the memory cell is determined by the bulk resistance of the chalcogenide element. Because the different solid-state phases of the chalcogenide have different resistivity, the bulk resistance of the chalcogenide element indicates the amount of the chalcogenide element in a selected phase state.
The problem of applying current at sufficient current densities to cause the phase change in the chalcogenide element is reflected in the design of the memory cells. Typically, relatively complex structures are utilized to form small pores in the current path that is coupled to the chalcogenide element. Current is concentrated through the small pores to induce a locally high current density in the chalcogenide element.
The complex structures utilized to form the pores, and other aspects of chalcogenide based memory cells, have required relatively large cell sizes to implement. Furthermore, complex structures can affect the reliability of the memory devices. Large cell sizes limit the density of the memory device, and increase its cost. Likewise, reliability in manufacturing is critical to successful commercial application of memory devices. High-density, self aligned memory cells have been manufactured for other types of storage technologies, such as the vertically stacked, non-volatile memory described in Johnson et al., U.S. Pat. No. 6,185,122. However, such high-density techniques have not been applied to phase change memory cells.
Accordingly, it is desirable to provide phase change memory cell structures and devices with smaller sizes. Furthermore, it is desirable to provide methods for manufacturing such devices, which are efficient and result in reliable structures.
The present invention provides a self-aligned, nonvolatile memory structure based upon phase change materials, including chalcogenides, and methods for manufacturing integrated circuit devices using the structure. The memory structure can be made within a very small area on an integrated circuit. For a preferred implementation, the area required for each memory cell in an array is about 4F2, where F is equal to the minimum line width for the manufacturing process. Thus, for processes having a minimum line width of 0.1 microns, the memory cell area is about 0.04 microns squared.
Furthermore, the manufacturing process results in self-aligned memory cells requiring only two array-related masks defining the bit lines and word lines. Memory cells are defined at intersections of bit lines and word lines, and have dimensions that are defined by the widths of the bit lines and word lines in a self-aligned process.
The use of phase change materials including chalcogenides, in the structure of the present invention provides for high-density non-volatile and programmable memory devices.
According to one embodiment of the invention, a method for manufacturing a memory device is provided. The method includes forming a multi-layer film on a surface of a substrate, where the multi-layer film includes a first conductive layer, a layer or layers of materials selected for formation of a selection device, and a layer or layers of materials selected for formation of the phase change memory element. The first array-related mask is applied to define a first plurality of lines extending in a first direction. Gaps are etched through the multi-layer film in according to the mask pattern to define the first plurality of lines. An insulating material is used to fill the gaps between the lines in the first plurality of lines.
A second conductive layer is formed over the first plurality of lines and insulating material in the gaps, to form a multi-layer composite. A second array-related mask is applied to define a second plurality of lines extending in a second direction so that the first and second pluralities of lines intersect. Gaps are etched into the multi-layer composite according to the second mask pattern to define the second plurality of lines. The gaps are etched between the second plurality of lines, and extend through the multi-layer composite to the first conductive layer, without removing the first conductor layer.
As a result of the etching steps, self-aligned stacks are formed by remaining portions of said layer or layers of materials selected for formation of a selection device, and said layer or layers of materials selected for formation of a phase change memory element. The selection device and phase change memory element in the self-aligned stacks are in electrical contact with the first plurality of lines in the first conductive layer, and the second plurality of lines remaining from the second conductive layer.
In some embodiments of the invention, the layer or layers of material selected for formation of a selection device comprise a first polysilicon layer with p-type dopant and a second polysilicon layer with n-type dopant adapted for formation of a diode.
Also, in some embodiments of the invention, the layer or layers of material selected for formation of a phase change memory element comprise a layer of chalcogenide. Further, in some embodiments, an intermediate layer is formed between the layer or layers of material selected for formation of a selection device, and the layer of phase change material. In various embodiments, the intermediate layer acts as a barrier to electromigration and diffusion of material between the materials used for the selection device, and the phase change material.
The phase change material has a first phase having a lower resistance, and a second phase having a higher resistance. Also, in various embodiments, the intermediate layer has a resistance that is greater than the higher resistance of the phase change material in the second phase. In this way, the intermediate layer acts as a resistive heating plate to facilitate phase change in the phase change material adjacent the barrier layer.
The present invention also provides a novel memory device. The memory device comprises a substrate. A first plurality of conductive lines on the substrate extend in a first direction. A second plurality of conductive lines above the first plurality of conductive lines, extend in a second direction, and cross over the first plurality of conductive lines at intersections. A plurality of memory cells are interposed at said intersections between, and in electrical contact with, the first and second pluralities of conductive lines. The memory cells comprise self-aligned structures including a selection device and a phase change memory element, vertically arranged at the intersections.
In embodiments of the present invention, the selection device comprises a diode. The phase change memory element comprises a chalcogenide body in various embodiments. In one preferred embodiment, the chalcogenide body comprises a thin film having substantially uniform thickness across the area of the intersection.
In one embodiment, the self-aligned structure comprises a first polysilicon layer and a second polysilicon layer adapted to form the selection device, an intermediate heating/barrier plate layer, and a layer of phase change material. The intermediate layer comprises a barrier to at least one of diffusion and electromigration. In one embodiment, the intermediate layer has a first resistance, and the layer of phase change material has a first state with a first lower resistance, and a second state with a second higher resistance. The first resistance of the intermediate layer is higher than the second higher resistance of the phase change material in the second state, so that the intermediate layer acts as a heating plate facilitating phase change adjacent to barrier layer.
In various embodiments, the phase change memory element is adapted to store more than one bit by assuming more than two bulk resistance states in response to programming current or other programming stimulus.
The memory array of the present invention is formed on a substrate. In some embodiments, the substrate is an integrated circuit device having an insulating layer on the surface. The memory array is manufactured on top of insulating layer, and has contacts to the circuitry integrated into substrate. Preferably, the circuitry integrated into the substrate includes support circuitry for the memory array, including address decoders, sense amplifiers, voltage sources and alike, manufactured for example with conventional CMOS technology. In other embodiments, the circuitry integrated into the substrate may include system-on-a-chip components, including for example, a processor core and other logic.
Accordingly, the present invention provides a unique memory cell that combines polysilicon junctions and chalcogenide memory elements, and a method for manufacturing the memory device comprising the unique cells. The new memory device can be programmed and erased by applying suitable voltage and current to change the resistance of the chalcogenide memory elements. Only two array-related masks are needed to make a memory, and the resulting memory cells are fully self-aligned with the word lines and bit lines of the array. Furthermore, the area within the array for each of the resulting memory cells is only 4F2, where F is the minimum line width for the manufacturing process.